From 2a6288d9b93f5b48782cac76d21f696bf5184cce Mon Sep 17 00:00:00 2001 From: Alyssa Ross Date: Wed, 27 Apr 2022 14:04:08 +0000 Subject: lib.systems: add riscv{32,64} sets and filters For other platforms like Intel and ARM, we can do e.g. lib.platforms.aarch64 to get only the 64-bit ARM platorms, but until now there were no equivalents for RISC-V. --- lib/systems/doubles.nix | 2 ++ lib/systems/inspect.nix | 2 ++ 2 files changed, 4 insertions(+) (limited to 'lib/systems') diff --git a/lib/systems/doubles.nix b/lib/systems/doubles.nix index 27cdaf6a7233b..3cdebbc07c1fa 100644 --- a/lib/systems/doubles.nix +++ b/lib/systems/doubles.nix @@ -74,6 +74,8 @@ in { mips = filterDoubles predicates.isMips; mmix = filterDoubles predicates.isMmix; riscv = filterDoubles predicates.isRiscV; + riscv32 = filterDoubles predicates.isRiscV32; + riscv64 = filterDoubles predicates.isRiscV64; vc4 = filterDoubles predicates.isVc4; or1k = filterDoubles predicates.isOr1k; m68k = filterDoubles predicates.isM68k; diff --git a/lib/systems/inspect.nix b/lib/systems/inspect.nix index 0ebaeba7bd897..27c25deafec38 100644 --- a/lib/systems/inspect.nix +++ b/lib/systems/inspect.nix @@ -24,6 +24,8 @@ rec { isMips64n64 = { cpu = { family = "mips"; bits = 64; }; abi = { abi = "64"; }; }; isMmix = { cpu = { family = "mmix"; }; }; isRiscV = { cpu = { family = "riscv"; }; }; + isRiscV32 = { cpu = { family = "riscv"; bits = 32; }; }; + isRiscV64 = { cpu = { family = "riscv"; bits = 64; }; }; isSparc = { cpu = { family = "sparc"; }; }; isWasm = { cpu = { family = "wasm"; }; }; isMsp430 = { cpu = { family = "msp430"; }; }; -- cgit 1.4.1