diff options
| author | Fabián Heredia Montiel <fabianhjr@protonmail.com> | 2020-12-23 18:02:10 -0600 |
|---|---|---|
| committer | Fabián Heredia Montiel <fabianhjr@protonmail.com> | 2020-12-23 18:57:59 -0600 |
| commit | 2a9ac172c1b979504b165830ef8e374f2efc3051 (patch) | |
| tree | c31ab82fb3a0e5bc132fbab0eb870607ba0b1977 /lib/systems | |
| parent | 57a787c9fa91f149c86a1ce83d57e07cfa589e07 (diff) | |
lib.systems: update processor architecture info
Diffstat (limited to 'lib/systems')
| -rw-r--r-- | lib/systems/architectures.nix | 44 |
1 files changed, 37 insertions, 7 deletions
diff --git a/lib/systems/architectures.nix b/lib/systems/architectures.nix index bfecaec1ae889..8e3a56b0d7c9c 100644 --- a/lib/systems/architectures.nix +++ b/lib/systems/architectures.nix @@ -12,6 +12,12 @@ rec { broadwell = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" "avx2" "fma" ]; skylake = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" "avx2" "fma" ]; skylake-avx512 = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" "avx2" "avx512" "fma" ]; + cannonlake = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" "avx2" "avx512" "fma" ]; + icelake-client = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" "avx2" "avx512" "fma" ]; + icelake-server = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" "avx2" "avx512" "fma" ]; + cascadelake = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" "avx2" "avx512" "fma" ]; + cooperlake = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" "avx2" "avx512" "fma" ]; + tigerlake = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" "avx2" "avx512" "fma" ]; # x86_64 AMD btver1 = [ "sse3" "ssse3" "sse4_1" "sse4_2" ]; btver2 = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" ]; @@ -21,6 +27,7 @@ rec { bdver4 = [ "sse3" "ssse3" "sse4_1" "sse4_2" "sse4a" "aes" "avx" "avx2" "fma" "fma4" ]; znver1 = [ "sse3" "ssse3" "sse4_1" "sse4_2" "sse4a" "aes" "avx" "avx2" "fma" ]; znver2 = [ "sse3" "ssse3" "sse4_1" "sse4_2" "sse4a" "aes" "avx" "avx2" "fma" ]; + znver3 = [ "sse3" "ssse3" "sse4_1" "sse4_2" "sse4a" "aes" "avx" "avx2" "fma" ]; # other armv5te = [ ]; armv6 = [ ]; @@ -41,15 +48,38 @@ rec { broadwell = [ "haswell" ] ++ inferiors.haswell; skylake = [ "broadwell" ] ++ inferiors.broadwell; skylake-avx512 = [ "skylake" ] ++ inferiors.skylake; + # x86_64 AMD + # TODO: fill this (need testing) btver1 = [ ]; - btver2 = [ ]; # TODO: fill this (need testing) - bdver1 = [ ]; # TODO: fill this (need testing) - bdver2 = [ ]; # TODO: fill this (need testing) - bdver3 = [ ]; # TODO: fill this (need testing) - bdver4 = [ ]; # TODO: fill this (need testing) - znver1 = [ ]; # TODO: fill this (need testing) - znver2 = [ ]; # TODO: fill this (need testing) + btver2 = [ ]; + bdver1 = [ ]; + bdver2 = [ ]; + bdver3 = [ ]; + bdver4 = [ ]; + # Regarding `skylake` as inferior of `znver1`, there are reports of + # successful usage by Gentoo users and Phoronix benchmarking of different + # `-march` targets. + # + # The GCC documentation on extensions used and wikichip documentation + # regarding supperted extensions on znver1 and skylake was used to create + # this partial order. + # + # Note: + # + # - The succesors of `skylake` (`cannonlake`, `icelake`, etc) use `avx512` + # which no current AMD Zen michroarch support. + # - `znver1` uses `ABM`, `CLZERO`, `CX16`, `MWAITX`, and `SSE4A` which no + # current Intel microarch support. + # + # https://www.phoronix.com/scan.php?page=article&item=amd-znver3-gcc11&num=1 + # https://gcc.gnu.org/onlinedocs/gcc/x86-Options.html + # https://en.wikichip.org/wiki/amd/microarchitectures/zen + # https://en.wikichip.org/wiki/intel/microarchitectures/skylake + znver1 = [ "skylake" ] ++ inferiors.skylake; + znver2 = [ "znver1" ] ++ inferiors.znver1; + znver3 = [ "znver2" ] ++ inferiors.znver2; + # other armv5te = [ ]; armv6 = [ ]; |