diff options
| author | Fabián Heredia Montiel <fabianhjr@protonmail.com> | 2022-11-27 23:18:20 +0100 |
|---|---|---|
| committer | Fabián Heredia Montiel <fabianhjr@protonmail.com> | 2023-06-24 00:50:40 -0600 |
| commit | 79dfc50bb8fa528b14675acbb55c4845c346f945 (patch) | |
| tree | 3586c376d66468f3d63d6d2931301ace07e6b3a6 /lib | |
| parent | 998b322eac8d3900304554a77e43c209098b8125 (diff) | |
lib.systems.architectures: add microarchitecture levels
Variation on: - https://github.com/NixOS/nixpkgs/pull/208398 - https://github.com/NixOS/nixpkgs/pull/224978 Co-authored-by: Sandro Jäckel <sandro.jaeckel@gmail.com> Co-authored-by: Shawn8901 <shawn8901@googlemail.com> Co-authored-by: AveryanAlex <alex@averyan.ru>
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/systems/architectures.nix | 39 |
1 files changed, 28 insertions, 11 deletions
diff --git a/lib/systems/architectures.nix b/lib/systems/architectures.nix index 11668ae59a71a..9be8c80e3f117 100644 --- a/lib/systems/architectures.nix +++ b/lib/systems/architectures.nix @@ -3,8 +3,15 @@ rec { # gcc.arch to its features (as in /proc/cpuinfo) features = { + # x86_64 Generic + # Spec: https://gitlab.com/x86-psABIs/x86-64-ABI/ default = [ ]; + x86-64 = [ ]; + x86-64-v2 = [ "sse3" "ssse3" "sse4_1" "sse4_2" ]; + x86-64-v3 = [ "sse3" "ssse3" "sse4_1" "sse4_2" "avx" "avx2" "fma" ]; + x86-64-v4 = [ "sse3" "ssse3" "sse4_1" "sse4_2" "avx" "avx2" "avx512" "fma" ]; # x86_64 Intel + nehalem = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" ]; westmere = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" ]; sandybridge = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" ]; ivybridge = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" ]; @@ -41,22 +48,32 @@ rec { # a superior CPU has all the features of an inferior and is able to build and test code for it inferiors = { + # x86_64 Generic + default = [ ]; + x86-64 = [ ]; + x86-64-v2 = [ "x86-64" ]; + x86-64-v3 = [ "x86-64-v2" ] ++ inferiors.x86-64-v2; + x86-64-v4 = [ "x86-64-v3" ] ++ inferiors.x86-64-v3; + # x86_64 Intel # https://gcc.gnu.org/onlinedocs/gcc/x86-Options.html - default = [ ]; - westmere = [ ]; - sandybridge = [ "westmere" ] ++ inferiors.westmere; - ivybridge = [ "sandybridge" ] ++ inferiors.sandybridge; - haswell = [ "ivybridge" ] ++ inferiors.ivybridge; - broadwell = [ "haswell" ] ++ inferiors.haswell; - skylake = [ "broadwell" ] ++ inferiors.broadwell; - skylake-avx512 = [ "skylake" ] ++ inferiors.skylake; + nehalem = [ "x86-64-v2" ] ++ inferiors.x86-64-v2; + westmere = [ "nehalem" ] ++ inferiors.nehalem; + sandybridge = [ "westmere" ] ++ inferiors.westmere; + ivybridge = [ "sandybridge" ] ++ inferiors.sandybridge; + + haswell = lib.unique ([ "ivybridge" "x86-64-v3" ] ++ inferiors.ivybridge ++ inferiors.x86-64-v3); + broadwell = [ "haswell" ] ++ inferiors.haswell; + skylake = [ "broadwell" ] ++ inferiors.broadwell; + + skylake-avx512 = lib.unique ([ "skylake" "x86-64-v4" ] ++ inferiors.skylake ++ inferiors.x86-64-v4); cannonlake = [ "skylake-avx512" ] ++ inferiors.skylake-avx512; icelake-client = [ "cannonlake" ] ++ inferiors.cannonlake; icelake-server = [ "icelake-client" ] ++ inferiors.icelake-client; - cascadelake = [ "skylake-avx512" ] ++ inferiors.cannonlake; + cascadelake = [ "cannonlake" ] ++ inferiors.cannonlake; cooperlake = [ "cascadelake" ] ++ inferiors.cascadelake; tigerlake = [ "icelake-server" ] ++ inferiors.icelake-server; + # CX16 does not exist on alderlake, while it does on nearly all other intel CPUs alderlake = [ ]; @@ -87,10 +104,10 @@ rec { # https://gcc.gnu.org/onlinedocs/gcc/x86-Options.html # https://en.wikichip.org/wiki/amd/microarchitectures/zen # https://en.wikichip.org/wiki/intel/microarchitectures/skylake - znver1 = [ "skylake" ] ++ inferiors.skylake; + znver1 = [ "skylake" ] ++ inferiors.skylake; # Includes haswell and x86-64-v3 znver2 = [ "znver1" ] ++ inferiors.znver1; znver3 = [ "znver2" ] ++ inferiors.znver2; - znver4 = [ "znver3" ] ++ inferiors.znver3; + znver4 = lib.unique ([ "znver3" "x86-64-v4" ] ++ inferiors.znver3 ++ inferiors.x86-64-v4); # other armv5te = [ ]; |