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authorOtavio Salvador <otavio@ossystems.com.br>2023-10-30 18:50:39 -0300
committerAnderson Torres <torres.anderson.85@protonmail.com>2023-11-13 20:58:12 -0300
commit2318de70529d5b15293037943e470c1d77c4cb2c (patch)
tree08574e5443b71c86807e7a61dd0f7d01e4178f65 /nixos/doc/manual
parent455d485fd6f75a2e97689d2c37875423016d99b0 (diff)
docker: move default from 20.10 to 24
Docker CE 20.10 seems to stop receiving security updates and bug fixes
after December 10, 2023[1].

1. https://github.com/moby/moby/discussions/45104

There is public commitment for longer maintenance and then it seems
risky to default to it during 23.11 life-cycle.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Diffstat (limited to 'nixos/doc/manual')
-rw-r--r--nixos/doc/manual/release-notes/rl-2311.section.md2
1 files changed, 2 insertions, 0 deletions
diff --git a/nixos/doc/manual/release-notes/rl-2311.section.md b/nixos/doc/manual/release-notes/rl-2311.section.md
index f623d931b3a93..051c0e7c663be 100644
--- a/nixos/doc/manual/release-notes/rl-2311.section.md
+++ b/nixos/doc/manual/release-notes/rl-2311.section.md
@@ -565,4 +565,6 @@ The module update takes care of the new config syntax and the data itself (user
 
 - The Linux kernel module `msr` (see [`msr(4)`](https://man7.org/linux/man-pages/man4/msr.4.html)), which provides an interface to read and write the model-specific registers (MSRs) of an x86 CPU, can now be configured via `hardware.cpu.x86.msr`.
 
+- Docker now defaults to 24, as 20.10 is stopping to receive security updates and bug fixes after [December 10, 2023](https://github.com/moby/moby/discussions/45104).
+
 - There is a new NixOS option when writing NixOS tests `testing.initrdBackdoor`, that enables `backdoor.service` in initrd. Requires `boot.initrd.systemd.enable` to be enabled. Boot will pause in stage 1 at `initrd.target`, and will listen for commands from the `Machine` python interface, just like stage 2 normally does. This enables commands to be sent to test and debug stage 1. Use `machine.switch_root()` to leave stage 1 and proceed to stage 2.