diff options
| author | Jack Leightcap <jack@leightcap.com> | 2023-05-06 12:35:27 -0400 |
|---|---|---|
| committer | Jack Leightcap <jack@leightcap.com> | 2023-05-06 12:35:27 -0400 |
| commit | 03ad8569fd648be154c4258d8d3c02ee7e28bed6 (patch) | |
| tree | e09ec4cacd1dacc1781b01e401eeb523124cc23a /pkgs/applications/science/electronics | |
| parent | e97667163ea4b9e17f2341c08c066ff47ce3722a (diff) | |
verilog-12.0: temp disable regression test suite
Signed-off-by: Jack Leightcap <jack@leightcap.com>
Diffstat (limited to 'pkgs/applications/science/electronics')
| -rw-r--r-- | pkgs/applications/science/electronics/verilog/default.nix | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/pkgs/applications/science/electronics/verilog/default.nix b/pkgs/applications/science/electronics/verilog/default.nix index 485bc27e801c1..bf55ec982ca58 100644 --- a/pkgs/applications/science/electronics/verilog/default.nix +++ b/pkgs/applications/science/electronics/verilog/default.nix @@ -44,8 +44,13 @@ stdenv.mkDerivation rec { enableParallelBuilding = true; + # NOTE(jleightcap): the `make check` target only runs a "Hello, World"-esque sanity check. + # the tests in the doInstallCheck phase run a full regression test suite. + # however, these tests currently fail upstream on aarch64 + # (see https://github.com/steveicarus/iverilog/issues/917) + # so disable the full suite for now. doCheck = true; - doInstallCheck = true; + doInstallCheck = false; nativeInstallCheckInputs = [ perl |