diff options
author | Matt Huszagh <huszaghmatt@gmail.com> | 2020-05-04 10:40:35 -0700 |
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committer | Matt Huszagh <huszaghmatt@gmail.com> | 2020-08-22 09:42:34 -0700 |
commit | 38aadfbbad493465323cf9295b87dc6084c973ad (patch) | |
tree | ffdcb666c5f19f0e52170feb50854ce39e140c20 /pkgs/applications/science | |
parent | d3dc37ac775a8853d345ef5b42604b28c63bc3d2 (diff) |
vhd2vl: init at unstable-2018-09-01
Diffstat (limited to 'pkgs/applications/science')
-rw-r--r-- | pkgs/applications/science/electronics/vhd2vl/default.nix | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/pkgs/applications/science/electronics/vhd2vl/default.nix b/pkgs/applications/science/electronics/vhd2vl/default.nix new file mode 100644 index 0000000000000..43dfdcabd02fc --- /dev/null +++ b/pkgs/applications/science/electronics/vhd2vl/default.nix @@ -0,0 +1,39 @@ +{ stdenv +, fetchFromGitHub +, bison +, flex +, verilog +}: + +stdenv.mkDerivation rec { + pname = "vhd2vl"; + version = "unstable-2018-09-01"; + + src = fetchFromGitHub { + owner = "ldoolitt"; + repo = pname; + rev = "37e3143395ce4e7d2f2e301e12a538caf52b983c"; + sha256 = "17va2pil4938j8c93anhy45zzgnvq3k71a7glj02synfrsv6fs8n"; + }; + + nativeBuildInputs = [ + bison + flex + ]; + + buildInputs = [ + verilog + ]; + + installPhase = '' + mkdir -p $out/bin + cp src/vhd2vl $out/bin/ + ''; + + meta = with stdenv.lib; { + description = "VHDL to Verilog converter"; + homepage = "https://github.com/ldoolitt/vhd2vl"; + license = licenses.gpl2Plus; + maintainers = with maintainers; [ matthuszagh ]; + }; +} |