about summary refs log tree commit diff
path: root/pkgs/development/compilers/gcc/patches/13/ICE-PR110280.patch
blob: 7338b3dd1ede37cbf0b34505be76d9575260666b (plain) (blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
From f4029de35fb1b293a4fd586574b1b4b73ddf7880 Mon Sep 17 00:00:00 2001
From: Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
Date: Wed, 26 Jul 2023 22:36:26 +0530
Subject: [PATCH] [aarch64/match.pd] Fix ICE observed in PR110280.

gcc/ChangeLog:
	PR tree-optimization/110280
	* match.pd (vec_perm_expr(v, v, mask) -> v): Explicitly build vector
	using build_vector_from_val with the element of input operand, and
	mask's type if operand and mask's types don't match.

gcc/testsuite/ChangeLog:
	PR tree-optimization/110280
	* gcc.target/aarch64/sve/pr110280.c: New test.

(cherry picked from commit 85d8e0d8d5342ec8b4e6a54e22741c30b33c6f04)
---
 gcc/match.pd                                    |  9 ++++++++-
 gcc/testsuite/gcc.target/aarch64/sve/pr110280.c | 12 ++++++++++++
 2 files changed, 20 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/pr110280.c

diff --git a/gcc/match.pd b/gcc/match.pd
index 9118244825054..c3bb4fbc0a7a2 100644
--- a/gcc/match.pd
+++ b/gcc/match.pd
@@ -8292,7 +8292,14 @@ and,
 
 (simplify
  (vec_perm vec_same_elem_p@0 @0 @1)
- @0)
+ (if (types_match (type, TREE_TYPE (@0)))
+  @0
+  (with
+   {
+     tree elem = uniform_vector_p (@0);
+   }
+   (if (elem)
+    { build_vector_from_val (type, elem); }))))
 
 /* Push VEC_PERM earlier if that may help FMA perception (PR101895).  */
 (simplify
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr110280.c b/gcc/testsuite/gcc.target/aarch64/sve/pr110280.c
new file mode 100644
index 0000000000000..d3279f383629f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pr110280.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -fdump-tree-optimized" } */
+
+#include "arm_sve.h"
+
+svuint32_t l()
+{
+  _Alignas(16) const unsigned int lanes[4] = {0, 0, 0, 0};
+  return svld1rq_u32(svptrue_b8(), lanes);
+}
+
+/* { dg-final { scan-tree-dump-not "VEC_PERM_EXPR" "optimized" } } */